In synchronous memory devices, such as synchronous dynamic random access memory (“SDRAM”) devices, the memory device is clocked by an external clock signal to allow operations to be performed at predetermined times relative to the rising and falling edges of the applied clock signal. For example, write data signals are applied to data bus terminals of the memory device in synchronism with the external clock signal, and the memory device must latch these data signals at the proper times to successfully capture the data signals. In the present description, “external” is used to refer to signals and operations outside of the memory device, and “internal” to refer to signals and operations within the memory device.
In a conventional SDRAM device, data drivers in the memory device may operate in either of two modes. In the first mode, known as the center tapped termination (“CTT”) mode, the memory devices biases the data bus terminals to a voltage intermediate high and low voltages corresponding to logic levels between which the terminals are switched to output read data signals. These high and low voltages are typically a supply voltage VCC and ground, respectively, and the CTT termination voltage is VCC/2. When read data signals are output from the memory device, the memory device drives the data bus terminals from VCC/2 to either VCC or ground depending on whether the corresponding read data bits are “1” or “0,” respectively. When write data signals are to be applied to the data bus terminals, the data bus terminals are biased to VCC/2. The externally applied write data signals applied to the data bus terminals drive the data bus terminals from VCC/2 to either VCC or ground depending on whether the corresponding write data bits are “1” or “0,” respectively. One set of read data signals are generally output from the memory device and one set of write data signals are generally applied to the memory device in synchronism with the rising edge of the clock signal. However, in double-data rate (“DDR”) memory devices, one set of read data signals are output from the memory device and one set of write data signals are applied to the memory device in synchronism with both the rising edge and the falling edge of the clock signal. When the memory device is inactive, the memory device does not bias the data bus terminals, but they are left at a high impedance and biased to VCC/2 by external circuitry.
In the other mode, known as the default high (“VDD”) mode, the data bus terminals are biased to VCC when data are to be either written to or read from the memory device. More specifically, the data bus terminals are biased to VCC during a preamble occurring before data are to be read from or written to the memory device, and during a postamble occurring after data have been read from or written to the memory device. The duration of the preamble is typically one-clock period, and the duration of the postamble is typically one-half clock period. When read data signals are output from the memory device, the data bus terminals are driven from VCC to ground if the corresponding read data bits are “0.” If the corresponding read data bits are “1,” the voltage at the data bus terminals remains at VCC. Write data signals applied to the data bus terminals drive the data bus terminals to ground if the corresponding write data bits are “0,” but maintain the data bus terminals at VCC if the corresponding write data bits are “1.” Again, when the memory device is inactive, the memory device does not bias the data bus terminals, but they are left at a high impedance and biased to VCC by external circuitry.
Another variation in the operating characteristics of memory device data bus terminals is the input and output impedance of the terminals. The input impedance of the data bus terminals affects the amount of current required to drive the data bus terminals to voltages corresponding to the two logic levels as well as the switching characteristics of the data bus terminals. Generally, a lower input impedance requires more current to drive the data bus terminals high and low, but it allows the terminals to be switched at a faster rate. The output impedance of the data bus terminals affects the “drive strength” of the memory device, i.e., the ability of the memory device to drive components connected to the data bus terminals. Again, a lower output impedance can require more current, but it can allow the data bus terminals to be switched at a faster rate.
In the past, the operating mode and input and output impedance of memory device data terminals were determined at the time memory devices were manufactured, although in some cases, the operating mode and/or impedance could be selected by opening or closing programmable links during manufacture. More recently, memory devices have been manufactured with an extended load mode register that includes an output drive strength bit. The drive strength bit can be programmed so that read data drivers operate in either a low impedance, full-drive mode or a high impedance, reduced-drive mode of operation. A memory controller typically sets the output drive strength bit in the extended load mode register via a load mode register command to thereby place the data driver in the desired operating mode. The data driver is typically placed in the full-drive mode when the DDR SDRAM device is being utilized in a conventional application, such as on a conventional memory module. The data driver may be placed in the reduced-drive mode when the DDR SDRAM device is being utilized in a point-to-point application, such as on a graphics card. During the full-drive mode, the data driver provides sufficient current to drive the DQ signals to full-range voltages for a particular loading of the data bus, while during the reduced-drive mode the driver provides a reduced current to drive the DQ signals to reduced voltages given the same loading of the data bus.
Although conventional memory devices, such as DDR SDRAM devices, allow limited user programmability of the output impedance of data bus terminals, they do not allow user programmability of the operating mode of the data bus terminals, including the establishment of preamble and postamble conditions in the VDD mode, nor do they allow adjustment of the input or termination impedance when write data signals are being coupled to either the memory device or to another memory device that is connected to a common bus.
There is therefore a need for a system and method to allow a user more complete programmability of the operating mode and impedance of memory device data bus terminals.